Next, we design a number of specific combinatorial and sequential circuits, which will be the building blocks of a simple computer:
Counter with clear
A counter with clear is a sequential circuit with 1 input and n outputs. It differs from an ordinary counter in that it has an input that sets the contents of the counter to 0.
Here is a state table for a 4-bit counter:
cl o3 o2 o1 o0 | o3' o2' o1' o0'
--------------------------------
0 0 0 0 0 | 0 0 0 1
0 0 0 0 1 | 0 0 1 0
0 0 0 1 0 | 0 0 1 1
0 0 0 1 1 | 0 1 0 0
0 0 1 0 0 | 0 1 0 1
0 0 1 0 1 | 0 1 1 0
0 0 1 1 0 | 0 1 1 1
0 0 1 1 1 | 1 0 0 0
0 1 0 0 0 | 1 0 0 1
0 1 0 0 1 | 1 0 1 0
0 1 0 1 0 | 1 0 1 1
0 1 0 1 1 | 1 1 0 0
0 1 1 0 0 | 1 1 0 1
0 1 1 0 1 | 1 1 1 0
0 1 1 1 0 | 1 1 1 1
0 1 1 1 1 | 0 0 0 0
1 0 0 0 0 | 0 0 0 0
1 0 0 0 1 | 0 0 0 0
1 0 0 1 0 | 0 0 0 0
1 0 0 1 1 | 0 0 0 0
1 0 1 0 0 | 0 0 0 0
1 0 1 0 1 | 0 0 0 0
1 0 1 1 0 | 0 0 0 0
1 0 1 1 1 | 0 0 0 0
1 1 0 0 0 | 0 0 0 0
1 1 0 0 1 | 0 0 0 0
1 1 0 1 0 | 0 0 0 0
1 1 0 1 1 | 0 0 0 0
1 1 1 0 0 | 0 0 0 0
1 1 1 0 1 | 0 0 0 0
1 1 1 1 0 | 0 0 0 0
1 1 1 1 1 | 0 0 0 0
As you can see, our conter behaves like an ordinary one when the cl signal is 0, and always goes to 0 when the cl signal is 1.
Counter register
A counter register is a sequential circuit with n + 1 inputs and n outputs. It differs from an ordinary counter in that it can also function as a register. It differes from a register in that when not explictly loaded, it works as a counter, rather than maintaining its previous value.
Here is a state table (abbreviated) for a 4-bit counter register:
ld i3 i2 i1 i0 o3 o2 o1 o0 | o3' o2' o1' o0'
--------------------------------------------
0 - - - - 0 0 0 0 | 0 0 0 1
0 - - - - 0 0 0 1 | 0 0 1 0
0 - - - - 0 0 1 0 | 0 0 1 1
0 - - - - 0 0 1 1 | 0 1 0 0
0 - - - - 0 1 0 0 | 0 1 0 1
0 - - - - 0 1 0 1 | 0 1 1 0
0 - - - - 0 1 1 0 | 0 1 1 1
0 - - - - 0 1 1 1 | 1 0 0 0
0 - - - - 1 0 0 0 | 1 0 0 1
0 - - - - 1 0 0 1 | 1 0 1 0
0 - - - - 1 0 1 0 | 1 0 1 1
0 - - - - 1 0 1 1 | 1 1 0 0
0 - - - - 1 1 0 0 | 1 1 0 1
0 - - - - 1 1 0 1 | 1 1 1 0
0 - - - - 1 1 1 0 | 1 1 1 1
0 - - - - 1 1 1 1 | 0 0 0 0
1 c3 c2 c1 c0 - - - - | c3 c2 c1 c0
As you can see, the counter register behaves like an ordinary counter when the ld signal is 0 and as a register when the ld signal is 1.
Counter register with clear
A counter register with clear is a sequential circuit with n + 2 inputs and n outputs. It differs from an ordinary counter register in that it also has a signal cl for clearing the contents.
It is a matter of taste what we want the circuit to do when both the ld and the cl signals are 1. In our application, we want the cl signal to take priority over the ld signal.
Here is a state table (abbreviated) for a 4-bit counter register with clear:
cl ld i3 i2 i1 i0 o3 o2 o1 o0 | o3' o2' o1' o0'
----------------------------------------------
0 0 - - - - 0 0 0 0 | 0 0 0 1
0 0 - - - - 0 0 0 1 | 0 0 1 0
0 0 - - - - 0 0 1 0 | 0 0 1 1
0 0 - - - - 0 0 1 1 | 0 1 0 0
0 0 - - - - 0 1 0 0 | 0 1 0 1
0 0 - - - - 0 1 0 1 | 0 1 1 0
0 0 - - - - 0 1 1 0 | 0 1 1 1
0 0 - - - - 0 1 1 1 | 1 0 0 0
0 0 - - - - 1 0 0 0 | 1 0 0 1
0 0 - - - - 1 0 0 1 | 1 0 1 0
0 0 - - - - 1 0 1 0 | 1 0 1 1
0 0 - - - - 1 0 1 1 | 1 1 0 0
0 0 - - - - 1 1 0 0 | 1 1 0 1
0 0 - - - - 1 1 0 1 | 1 1 1 0
0 0 - - - - 1 1 1 0 | 1 1 1 1
0 0 - - - - 1 1 1 1 | 0 0 0 0
0 1 c3 c2 c1 c0 - - - - | c3 c2 c1 c0
1 - - - - - - - - - | 0 0 0 0
This is exactly the circuit we will use for the micro program counter (or micro PC) of our simple example computer, except that in our example computer, the micro PC will be 6 bits wide instead of 4.
Counter register with clear and increment
A counter register with clear and increment is a sequential circuit with n + 3 inputs and n outputs. It differs from an ordinary counter register with clear in that it also has a signal incr for explicit counting. When the incr signal is 0 the output does not change, and when incr is 1, the circuit works as a counter.
For this circuit, we shall allow the ld signal to take priority over the incr signal, so that if both signals are 1, we load a new contents from the inputs. We shall also make the cl have the highest priority of all.
Here is a state table (abbreviated) for a 4-bit counter register with clear and increment:
cl ld incr i3 i2 i1 i0 o3 o2 o1 o0 | o3' o2' o1' o0'
---------------------------------------------------
0 0 0 - - - - c3 c2 c1 c0 | c3 c2 c1 c0
0 0 1 - - - - 0 0 0 0 | 0 0 0 1
0 0 1 - - - - 0 0 0 1 | 0 0 1 0
0 0 1 - - - - 0 0 1 0 | 0 0 1 1
0 0 1 - - - - 0 0 1 1 | 0 1 0 0
0 0 1 - - - - 0 1 0 0 | 0 1 0 1
0 0 1 - - - - 0 1 0 1 | 0 1 1 0
0 0 1 - - - - 0 1 1 0 | 0 1 1 1
0 0 1 - - - - 0 1 1 1 | 1 0 0 0
0 0 1 - - - - 1 0 0 0 | 1 0 0 1
0 0 1 - - - - 1 0 0 1 | 1 0 1 0
0 0 1 - - - - 1 0 1 0 | 1 0 1 1
0 0 1 - - - - 1 0 1 1 | 1 1 0 0
0 0 1 - - - - 1 1 0 0 | 1 1 0 1
0 0 1 - - - - 1 1 0 1 | 1 1 1 0
0 0 1 - - - - 1 1 1 0 | 1 1 1 1
0 0 1 - - - - 1 1 1 1 | 0 0 0 0
0 1 - c3 c2 c1 c0 - - - - | c3 c2 c1 c0
1 - - - - - - - - - - | 0 0 0 0
This is exactly the circuit we will use for the program counter (or PC) of our simple example computer, except that the PC in our computer will be 8 bits wide instead of 4.
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